UVM-Multi-Language Hands-On - Verilab

UVM-Multi-Language Hands-On - Verilab

UVM-Multi-Language Hands-On Thorsten Dworzak (Verilab GmbH) Angel Hidalga (Infineon Technologies AG) Accellera Systems Initiative 1 Introduction UVM-ML version 1.2

add-on library to UVM vendor/simulator independent Accelera Multi-Language working group easy integration of different HVLs (e, SV, SystemC) inter-language communication via TLM2 sockets Accellera Systems Initiative 2 Verification Focus (1) DUT is ARM CPU IP Different UVM-SV testbenches (DUT hierarchy) SystemC reference model joint development between software and hardware-verification team

Accellera Systems Initiative 3 Verification Focus (2) SystemC model must support 3 use-cases Accellera Systems Initiative 4 UVM Environment CPU SysC Model ISG and MEM IF Environment

CPU+Mem SysC Model fetch ISG Agent load D-Mem D-Mem store Scoreboard (Compare)

Instr IF Agent load+ store fetch DUT (CPU) state Accellera Systems Initiative PFU DEC

LSU EXC 5 REGFIILE state Data Agent C-Model Requirements

Specification compliance (Model and DUT output must match) Windows+Linux cross-platform development C++11 wrapped in System-C modules High performance (for stand-alone ISS) Support all use-cases with minimal code overlap More than one instance (careful with static classes) Error injection possible State roll-back support

Accellera Systems Initiative 6 Instruction Stream Generation (1) Instruction base class contains all properties that define an assembler instruction Specialized class defines required properties, e.g. opcode-size, legal source+destination registers. SV code generated from specification Accellera Systems Initiative 7 Instruction Stream Generation (2)

An ISG sequence contains an instruction item and several fields to control the item generation Dedicated sequences to write/read registers, establish fault handlers etc. Sequence API allows flexibility to do fully random instructions, specific instructions like LDR r0,[r5,r4,LSL #3], and anything in-between C-Model is used to predict next PC value (e.g. branch target) Opcodes known to be skipped will be set to BKPT to detect DUT bugs Code and data memory are separate, so no problem of stack running into code segment Accellera Systems Initiative 8 OSCI vs. ncsc OSCI 2.3.1 is reference implementation

Software team (Windows) relied on this Cadence implementation used by ncsc Easier build-flow, used by HW-verification team Compatibility is "good enough" OSCI-based flow can be used as fall-back solution Accellera Systems Initiative 9 Linux vs. Windows Collaborative effort of software and hw-verification team Software team used MS Visual Studio UVM testbench not available

Large suite of unit tests based on Google Test ensured up-front quality Several Jenkins projects continuously checked quality metrics e.g. make sure code-base compiles with gcc Software team followed Agile (Scrum) flow while HW-verification team uses traditional waterfall model Different SCMs Accellera Systems Initiative 10 ML Interface Selection Choice of interfaces according to requirements Accellera Systems Initiative

11 TLM2 sockets Use of SV type uvm_tlm_b__socket Multi-socket and passthrough sockets currently not supported Need to use default data type uvm_tlm_generic_payload Benefit from existing packing/serialization facilities of UVM-ML Created wrapper classes for the two types of sockets Encapsulates standard functionality (build, register, connect, ...) Unique namespace for b_transport() function in target socket Accellera Systems Initiative 12

TLM2 Generic Payload UVM-ML provides packing/serialization -> less code on SV and SystemC side Is intended to model memory-mapped bus transactions r/w, address, data, byte-enables Any missing functionality implemented as SV static functions Additional information transmitted via payload extensions Transaction privilege-level, initiator ID, embedded commands, ... Target response (type of error, busy status, ...) GP response_status field only used for TLM communication errors Accellera Systems Initiative 13

DPI-C Interface (1) Transmit integral types and structs across the language barrier Export SV methods called from C++ export "DPI-C" function cExpReqSysRst(); extern "C" void cExpReqSysRst(char modelType); function bit cExpReqSysRst(input byte modelType); ... endfunction

Tasks may consume time extern "C" void cExpSync(); export "DPI-C" task cExpSync(); task cExpSync(); @(posedge clk); endtask Accellera Systems Initiative 14 DPI-C Interface (2) Import C++ methods called from SV

import "DPI-C" context task cImpInitCpu(); int cImpInitCpu() { ... } context as opposed to pure attribute allows C++ implementation to access objects other than input parameters (e.g. SystemC objects, call exported methods) Accellera Systems Initiative 15 Simulation Performance

Using UVM testbench that allows drop-in replacement of DUT with Cmodel, we can compare the performance Accellera Systems Initiative 16 Summary Successfully deployed UVM-ML in SystemC/SystemVerilog environment Not all SystemC features implemented Most initial tool problems solved UVM-ML reduces effort to cross the language boundaries

Accellera Systems Initiative 17 Questions, Comments? Accellera Systems Initiative 18

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