Introduction to CMOS VLSI Design Lecture 11: Adders
Introduction to CMOS VLSI Design Lecture 11: Adders David Harris Harvey Mudd College Spring 2004 Outline Single-bit Addition Carry-Ripple Adder Carry-Skip Adder Carry-Lookahead Adder Carry-Select Adder Carry-Increment Adder Tree Adder 11: Adders CMOS VLSI Design Slide 2 Single-Bit Addition A Half Adder S B 0 S S Cout C S B C 0 0
1 1 1 11: Adders CMOS VLSI Design Slide 4 PGK For a full adder, define what happens to carries Generate: Cout = 1 independent of C G= Propagate: Cout = C P= Kill: Cout = 0 independent of C K= 11: Adders CMOS VLSI Design Slide 5 PGK For a full adder, define what happens to carries Generate: Cout = 1 independent of C G=AB Propagate: Cout = C P=AB Kill: Cout = 0 independent of C K = ~A ~B 11: Adders CMOS VLSI Design Slide 6 Full Adder Design I Brute force implementation from eqns S A B C Cout MAJ ( A, B, C ) A A A S MAJ Cout
C A B C B C B C B A 11: Adders B A B A B C A B C B C S C B B A CMOS VLSI Design A B C A C A B Cout
B Slide 7 Full Adder Design II Factor S in terms of Cout S = ABC + (A + B + C)(~Cout) Critical path is usually C to Cout in ripple adder MINORITY A B C Cout S S Cout 11: Adders CMOS VLSI Design Slide 8 Layout Clever layout circumvents usual line of diffusion Use wide transistors on critical path Eliminate output inverters 11: Adders CMOS VLSI Design Slide 9 Full Adder Design III Complementary Pass Transistor Logic (CPL) Slightly faster, but more area B B A A B C B C B C
B C A S S A B C B C B C B C Cout Cout B B 11: Adders CMOS VLSI Design Slide 10 Full Adder Design IV Dual-rail domino Very fast, but large and power hungry Used in very fast multipliers C_h A_h B_h A_h C_l B_h A_l C_h B_h
A_h C_l B_l Cout _l A_l B_l B_l S_l 11: Adders Cout _h S_h C_h B_h A_l CMOS VLSI Design Slide 11 Carry Propagate Adders N-bit adder called CPA Each sum bit depends on all previous carries How do we compute all these carries quickly? AN...1 BN...1 Cout Cout + SN...1 11: Adders Cin Cin 00000 1111 +0000 1111 CMOS VLSI Design Cout 11111
1111 +0000 0000 Cin carries A4...1 B4...1 S4...1 Slide 12 Carry-Ripple Adder Simplest design: cascade full adders Critical path goes from Cin to Cout Design full adder to have fast carry delay A4 B4 Cout B3 C3 S4 11: Adders A3 A2 B2 C2 S3 A1 B1 Cin C1 S2 CMOS VLSI Design S1 Slide 13 Adder is Symmetric A Ci A B
FA Co Ci S B FA Co S S A B C i = S A B C i C o A B C i = Co A B Ci 11: Adders CMOS VLSI Design Slide 14 Inversions Critical path passes through majority gate Built from minority + inverter Eliminate inverter and use inverting full adder A4 B4 Cout B3 C3 S4 11: Adders A3 A2 B2 C2 S3 A1 B1 Cin C1 S2
CMOS VLSI Design S1 Slide 15 Generate / Propagate Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A B Kill = 16 CMOS VLSI Design AB Generate / Propagate Equations often factored into G and P Generate and propagate for groups spanning i:j Gi: j Pi: j 0 GCP 0:00:0 in Base case Gi:i Gi Pi:i Pi G0:0 G0 P0:0 P0 Sum: Si 11: Adders CMOS VLSI Design Slide 17 Generate / Propagate 11: Adders CMOS VLSI Design Slide 18 Generate / Propagate Equations often factored into G and P Generate and propagate for groups spanning i:j Gi: j Gi:k Pi:k Gk 1: j Pi: j Pi:k Pk 1: j 0 GCP
0:00:0 in Base case Gi:i Gi Ai Bi Pi:i Pi Ai Bi G0:0 G0 Cin P0:0 P0 0 Sum: Si Pi Gi 1:0 11: Adders CMOS VLSI Design Slide 19 PG Logic A4 B4 A3 B3 A2 B2 A1 B1 Cin 1: Bitwise PG logic G4 P4 G3 P3 G2 P2 G1 P1 G0 P0 2: Group PG logic
Slide 41 Tree Adder Taxonomy Ideal N-bit tree adder would have L = log N logic levels Fanout never exceeding 2 No more than one wiring track between levels Describe adder with 3-D taxonomy (l, f, t) Logic levels: L+l Fanout: 2f + 1 Wiring tracks: 2t Known tree adders sit on plane defined by l + f + t = L-1 11: Adders CMOS VLSI Design Slide 42 Tree Adder Taxonomy l (Logic Levels) 3 (7) f (Fanout) 2 (6) 3 (9) 1 (5) 2 (5) 1 (3) 0 (2) 0 (4) 0 (1) 1 (2) 2 (4) 3 (8) t (Wire Tracks) 11: Adders CMOS VLSI Design Slide 43 Tree Adder Taxonomy l (Logic Levels) 3 (7)
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