DOM Main Board Rev 3/Rev 4 Status

DOM Main Board Rev 3/Rev 4 Status

DOM Main Board Rev 3/Rev 4 Status December 2, 2003 Gerald Przybylski Lawrence Berkeley National Laboratory Major Rev 3 Goals Booting to 50C, or colder Memory Interface Layout PMT Waveform integrity: Ringing, Clamping, Baseline Bounce Component Substitutions Deferred: -- Front-End Pulser

-- Local Coincidence Were On Track Rev 3 First Items (4) Boot at -70C, measured by on-board sensor: from Flash and from Configuration Memory Memory test OK at -50C, at 40 MHz, long term... Good PMT waveforms. Good clamping. No bounce. Perfect MB to Delay board fit Power Under 3W (at CPU @ 80MHz & Memory @ 40MHz) 2 boards: -60C, 160 MHz CPU, 125 MHz Mem RAP at -60C Rev 3 Problems PC Fab House Testing Failure Shorts on Top Layer: 2 pcs. 4 shorts

Two New Schematic Errors (Mentor/EDIF) Loading/Bill-of-Materials errors Two Footprint errors (QFP-100, Oscillator) Minor, but Unsightly Quirks in Front-End Pulser Waveform - product/brand dependency - Suppressible Rev 4 Changes Component Value Changes -- optimizations -- schematic corrections

Power Supply Load Balancing (One trace, one resistor) On-Board LED Pulser Power (Several parts) Component Substitutions for Reliability, - A few; mainly inductors 99% finalized - Availability issues Front End Pulser Corrections Layout Design Rule Optimizations Open Issues Chevette vs. Buick vs. Cadillac quality PCBs (Class 1, 2, 3) Verification (Qualtest) Split between LBNL and UW e.g. Thermal Cycling: How many? What range? e.g. Vibration Testing: What acceleration? Where? e.g. Humidity: Will UW measure RH at -40C? at -70C?? in purged and sealed DOM (VPH2O 0.002mm [email protected] vs. 0.1mm [email protected] vs. 24mm [email protected])

>> No problem, says RI<< Design for EMS, when mature (what measure of maturity?) Late Breaking News Receiving & Testing 12 More Rev 3 Boards - 6 Evenstar boards, 6 Data Circuits boards - Looking good so far; Many loading changes in batch Rev 4 Schematic Updates In Progress - 90% of schematic pages to date - Few additional Components. - Working from Detailed List; Configuration Control Rev 4 schedule Ongoing test stand parallel development (STF) -- To be available 1/23 -- Move to room 50a-6105 11/21Modification Review/approval of Spreadsheet and File III

11/25 Design rules Review 12/15 - 12/19 line-by-line Reviews 12/24 - 1/6 Fab 1/7 - 1/20 Assembly 1/23 - 2/19 Acceptance Testing at LBNL (STF based) 2/20 First 20 cards to UW 2/23 - 5/21 integration at UW, verification testing at UW and LBNL The End Bob you can change this link to point to your copy of the changes spreadsheet Changes Spreadsheet Digital Optical Module Block Diagram

Trigger (2) FPGA Pulser 1 5 4 8 x16 Delay ATWD

x2 x0.25 ATWD 10b 10b 10b MUX OB-LED (n+1) (n1)

10b CPU DP Ram 40 MHz 1 megabaud DOR 8b x 2.6 x 9 fADC

ADC DAC LPF +/-5V, 3.3V, 2.5V, 1.8V DC-DC Configuration Device 32b LC 8Mbit

SDRAM 16Mb SDRAM 16Mb 20 MHz Oscillator Corning Frequency Ctl (was Toyocom) Monitor & Control DACs & ADCs

8b, 10b, 12b 16b CPLD PMT Power Flash Flash 4Mb 4Mb 8b Flasher Board 64 Bytes ATWD

Readout Engine Communications Engine DOM FPGA Block Diagram Control & Status Registers

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