CS152 Computer Organization and Design

CS152 Computer Organization and Design

CS152 Computer Architecture and Engineering Lecture 9 Designing Single Cycle Control CS152 Lec9.1 Recap: Summary from last time 5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic MIPS makes it easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Single cycle datapath CPI=1, Cycle Time = long! CS152 Lec9.2 Recap: The MIPS Instruction Formats All MIPS instructions are 32 bits long. The three instruction formats: 31 op 6 bits R-type I-type J-type 26 31 21 rs 5 bits 26 op 6 bits 31 16 rt 5 bits 21 rs 5 bits 11 rd 5 bits 6 shamt 5 bits 0 funct 6 bits

16 rt 5 bits 0 immediate 16 bits 26 op 6 bits 0 target address 26 bits The different fields are: op: operation of the instruction rs, rt, rd: the source and destination registers specifier shamt: shift amount funct: selects the variant of the operation in the op field address / immediate: address offset or immediate value target address: target address of the jump instruction CS152 Lec9.3 An Abstract View of the Implementation Control Ideal Instruction Memory Rd Rs 5 5 Instruction Address PC Rw Ra Rb 32 32-bit Registers Clk Conditions Rt 5 A 32 Clk Control Signals 32 32 ALU Next Address Instruction B

32 Data Address Data In Ideal Data Memory Data Out Clk Datapath CS152 Lec9.4 Recap: A Single Cycle Datapath Rs, Rt, Rd and Imed16 hardwired into datapath from Fetch Unit We have everything except control signals (underline) Todays lecture will show you how to generate the control signals Instruction<31:0> 1 Mux 0 RegWr 5 5 Rs 5 Rt Rt Zero ALUctr MemtoReg 0 32 Data In 32 ALUSrc ExtOp Imm16 Clk WrEn Adr 32 Mux 0 1 32 ALU 16

Extender imm16 32 Mux 32 Clk Rw Ra Rb 32 32-bit Registers busB 32 Rd MemWr busA busW Rs <0:15> Clk <11:15> RegDst Rt <21:25> Rd Instruction Fetch Unit <16:20> nPC_sel 1 Data Memory CS152 Lec9.5 Recap: Meaning of the Control Signals nPC_MUX_sel: 0 PC < PC + 4 1 PC < PC + 4 + SignExt(Im16) || 00 Later in lecture: higher-level connection between mux and branch cond nPC_MUX_sel Adr 4 00 Adder

PC Mux Adder PC Ext imm16 Inst Memory Clk CS152 Lec9.6 Recap: Meaning of the Control Signalszero, sign MemWr: ExtOp: ALUsrc: MemtoReg: 0 ALU; 1 Mem 0 regB; 1 immed ALUctr: add, sub, or RegDst RegWr 5 RegWr: 1 write register ALUctr 5 Rs MemWr MemtoReg 5 Rt 16 32 0 1 32 Data In 32 ExtOp ALUSrc Clk 32 0

Mux imm16 Extender Clk = Mux busA Rw Ra Rb 32 32-bit Registers busB 32 ALU 32 0 rt; 1 rd 0 1 busW RegDst: Equal Rd Rt 1 write memory WrEn Adr 1 Data Memory CS152 Lec9.7 RTL: The Add Instruction 31 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits 0

funct 6 bits add rd, rs, rt mem[PC] Fetch the instruction from memory R[rd] <- R[rs] + R[rt] The actual operation PC <- PC + 4 Calculate the next instructions address CS152 Lec9.8 Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction <- mem[PC] This is the same for all instructions Inst Memory Instruction<31:0> Adr nPC_MUX_sel 4 00 Adder imm16 PC Mux Adder PC Ext Clk CS152 Lec9.9 The Single Cycle Datapath during Add 31 26 21 16 11 op rs rt rd 6 0 shamt funct

R[rd] <- R[rs] + R[rt] 5 Zero ALU 16 Extender imm16 1 32 ExtOp = x Rd Clk Imm16 MemtoReg = 0 MemWr = 0 0 32 Data In 32 ALUSrc = 0 Rs WrEn Adr 32 Mux busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Rt <0:15> 5 ALUctr = Add Rt <11:15> 5 Rs Mux 32 Clk

Clk 1 Mux 0 RegWr = 1 busW Rt <16:20> RegDst = 1 Rd Instruction Fetch Unit <21:25> nPC_sel= +4 Instruction<31:0> 1 Data Memory CS152 Lec9.10 Instruction Fetch Unit at the End of Add PC <- PC + 4 This is the same for all instructions except: Branch and Jump Inst Memory Instruction<31:0> Adr nPC_MUX_sel Adder 0 PC Mux Adder imm16 00 4 1 Clk CS152 Lec9.11 The Single Cycle Datapath during Or Immediate 31 26 21 16 op rs

rt 0 immediate R[rt] <- R[rs] or ZeroExt[Imm16] Instruction<31:0> 1 Mux 0 RegWr = 5 Rt ALUctr = Zero 16 Extender imm16 1 32 ExtOp = Rd Clk Imm16 MemtoReg = MemWr = 0 32 Data In 32 ALUSrc = Rs WrEn Adr 32 Mux busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Mux 32 Clk 5

Rt ALU busW 5 Rs <0:15> Clk <11:15> RegDst = Rt <21:25> Rd Instruction Fetch Unit <16:20> nPC_sel = 1 Data Memory CS152 Lec9.12 The Single Cycle Datapath during Load 31 26 21 16 op rs rt 0 immediate R[rt] <- Data Memory {R[rs] + SignExt[imm16]} busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Rt Zero 32 ExtOp = 1 Imm16

MemtoReg = 1 MemWr = 0 0 32 Data In 32 ALUSrc = 1 Rd Clk Mux ALU 16 Extender imm16 1 Rs <0:15> 5 ALUctr = Add Rt <11:15> 5 Rs Mux 32 Clk Clk 1 Mux 0 RegWr = 1 5 busW Rt <16:20> RegDst = 0 Rd Instruction Fetch Unit <21:25> nPC_sel= +4 Instruction<31:0>

1 WrEn Adr Data Memory 32 CS152 Lec9.14 The Single Cycle Datapath during Store 31 26 21 16 op rs rt 0 immediate Data Memory {R[rs] + SignExt[imm16]} <- R[rt] Instruction<31:0> RegWr = 5 5 Rs 5 Rt Rt ALUctr = busA 0 1 32 ExtOp = MemWr = Clk Imm16 MemtoReg = 0 32 Data In 32 ALUSrc = Rd WrEn Adr 32

Mux 16 Extender imm16 32 Mux 32 Clk Rw Ra Rb 32 32-bit Registers busB 32 ALU busW Zero Rs <0:15> Clk 1 Mux 0 <11:15> Rt <21:25> RegDst = Rd Instruction Fetch Unit <16:20> nPC_sel = 1 Data Memory CS152 Lec9.15 The Single Cycle Datapath during Store 31 26 21 16 op rs rt 0

immediate Data Memory {R[rs] + SignExt[imm16]} <- R[rt] Zero ALU 16 Extender imm16 1 ExtOp = 1 Rd 32 Clk Imm16 MemtoReg = x MemWr = 1 0 32 Data In 32 ALUSrc = 1 Rs WrEn Adr 32 Mux busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Rt <0:15> 5 ALUctr = Add Rt <11:15> 5 Rs Mux 32 Clk

Clk 1 Mux 0 RegWr = 0 5 busW Rt <16:20> RegDst = x Rd Instruction Fetch Unit <21:25> nPC_sel= +4 Instruction<31:0> 1 Data Memory CS152 Lec9.16 The Single Cycle Datapath during Branch31 26 21 16 op rs rt 0 immediate if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 Instruction<31:0> 5 Rt ALUctr =Sub Zero ALU 16 Extender imm16 1 32 ExtOp = x Clk

Imm16 MemtoReg = x MemWr = 0 0 32 Data In 32 ALUSrc = 0 Rd WrEn Adr 32 Mux busA Rw Ra Rb 32 32 32-bit Registers busB 0 32 Rs <0:15> 5 Rt <11:15> 5 Rs Mux 32 Clk Clk 1 Mux 0 RegWr = 0 busW Rt <21:25> RegDst = x Rd Instruction Fetch Unit <16:20> nPC_sel= Br 1

Data Memory CS152 Lec9.17 Instruction Fetch Unit at the End of 26 21 16 Branch31 op rs rt 0 immediate if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4 Inst Memory nPC_sel Adr Zero nPC_MUX_sel 4 What is encoding of nPC_sel? Direct MUX select? Branch / not branch 0 00 Lets choose second option Adder PC Mux Adder imm16 Instruction<31:0> 1 nPC_sel 0 1 1 zero? x 0 1 MUX 0 0 1 Clk CS152 Lec9.18

Step 4: Given Datapath: RTL -> Control Instruction<31:0> Rd <0:15> Rs <11:15> Rt <16:20> Op Fun <21:25> Adr <21:25> Inst Memory Imm16 Control nPC_sel RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg Zero DATA PATH CS152 Lec9.19 A Summary of Control Signals inst Register Transfer ADD R[rd] < R[rs] + R[rt]; PC < PC + 4 ALUsrc = RegB, ALUctr = add, RegDst = rd, RegWr, nPC_sel = +4 SUB R[rd] < R[rs] R[rt]; PC < PC + 4 ALUsrc = RegB, ALUctr = sub, RegDst = rd, RegWr, nPC_sel = +4 ORi R[rt] < R[rs] + zero_ext(Imm16); PC < PC + 4 ALUsrc = Im, Extop = Z, ALUctr = or, RegDst = rt, RegWr, nPC_sel = +4 LOAD R[rt] < MEM[ R[rs] + sign_ext(Imm16)]; PC < PC + 4

ALUsrc = Im, Extop = Sn, ALUctr = add, MemtoReg, RegDst = rt, RegWr, nPC_sel = +4 STORE MEM[ R[rs] + sign_ext(Imm16)] < R[rs]; PC < PC + 4 ALUsrc = Im, Extop = Sn, ALUctr = add, MemWr, nPC_sel = +4 BEQ if ( R[rs] == R[rt] ) then PC < PC + sign_ext(Imm16)] || 00 else PC < PC + 4 nPC_sel = Br, ALUctr = sub CS152 Lec9.20 A Summary of the Control Signals See Appendix A func 10 0000 10 0010 We Dont Care :-) op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 add 1 0 sub 1 0 ori 0 1 lw 0 1 sw x 1 beq x 0 jump x x MemtoReg RegWrite MemWrite 0 1 0 0 1 0 0 1 0 1 1 0

x 0 1 x 0 0 x 0 0 nPCsel Jump ExtOp 0 0 x 0 0 x 0 0 0 0 0 1 0 0 1 1 0 x 0 1 x Add Subtract Or Add Add Subtract xxx RegDst ALUSrc ALUctr<2:0> 31 26 21 16 R-type op

rs rt I-type op rs rt J-type op 11 rd 6 shamt immediate target address 0 funct add, sub ori, lw, sw, beq jump CS152 Lec9.21 The Concept of Local Decoding op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type 1 0 ori 0 1 lw 0 1 sw x 1 beq x 0 jump x x MemtoReg RegWrite MemWrite 0 1

0 0 1 0 1 1 0 x 0 1 x 0 0 x 0 0 Branch Jump ExtOp 0 0 x 0 0 0 0 0 1 0 0 1 1 0 x 0 1 x Or Add Add Subtract xxx RegDst ALUSrc ALUop op 6 R-type Main Control

func 6 ALUop ALUctr 3 ALU N ALU Control (Local) CS152 Lec9.22 The Encoding of ALUop op 6 Main Control func 6 ALUop N ALU Control (Local) ALUctr 3 In this exercise, ALUop has to be 2 bits wide to represent: (1) R-type instructions I-type instructions that require the ALU to perform: - (2) Or, (3) Add, and (4) Subtract To implement the full MIPS ISA, ALUop has to be 3 bits to represent: (1) R-type instructions I-type instructions that require the ALU to perform: - (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi) ALUop (Symbolic) ALUop<2:0> R-type R-type 1 00 ori Or 0 10 lw Add 0 00 sw Add 0 00 beq jump Subtract xxx xxx 0 01 CS152 Lec9.23

The Decoding of the func Field func op 6 ALUop (Symbolic) R-type R-type ALUop<2:0> 31 R-type 1 00 26 op ALU Control (Local) 6 ALUop N Main Control 21 rs ori Or lw Add sw Add 0 10 0 00 0 00 16 rt ALUctr 3 11 rd beq jump Subtract xxx xxx 0 01 6 shamt 0 funct

P. 286 text: Instruction Operation add subtract and or set-on-less-than ALUctr ALU funct<5:0> 10 0000 10 0010 10 0100 10 0101 10 1010 ALUctr<2:0> 000 001 010 110 111 ALU Operation And Or Add Subtract Set-on-less-than CS152 Lec9.24 The Truth Table for ALUctr R-type ALUop (Symbolic) R-type ALUop<2:0> 1 00 ALUop bit<2> bit<1> bit<0> 0 0 0 ori Or 0 10 lw Add 0 00 sw Add 0 00 beq funct<3:0> 0000 0010 Instruction Op. add subtract 0100 0101

1010 and or set-on-less-than Subtract 0 01 func bit<3> bit<2> bit<1> bit<0> x x x x ALU Operation Add ALUctr bit<2> bit<1> bit<0> 0 1 0 0 0 1 x 1 x 1 x x x x 0 x x 0 x x 0 x x 0 Subtract Or Add 1 0 0 1 0 1 0 1 0 1 1 1

x x x x x x 0 0 0 0 1 1 1 0 0 0 0 1 Subtract And Or 1 0 0 1 0 0 0 0 1 1 x x 1 0 1 0 Set on < 1 1 1 CS152 Lec9.25 The Logic Equation for ALUctr<2> ALUop bit<2> bit<1> bit<0> 0 x 1

1 1 x x x x func bit<3> bit<2> bit<1> bit<0> x x x x 0 1 0 0 1 1 0 0 ALUctr<2> 1 1 1 This makes func<3> a dont care ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0> CS152 Lec9.26 The Logic Equation for ALUctr<1> ALUop bit<2> bit<1> bit<0> func bit<3> bit<2> bit<1> bit<0> ALUctr<1> 0 0 1 0 x x 0 1 x x x 0 x x 0 x x 0 x

x 0 1 1 1 1 1 x x x x 0 1 0 0 1 1 0 0 1 1 ALUctr<1> = !ALUop<2> & !ALUop<1> + ALUop<2> & !func<2> & !func<0> CS152 Lec9.27 The Logic Equation for ALUctr<0> ALUop bit<2> bit<1> bit<0> 0 1 1 1 x x x x x func bit<3> bit<2> bit<1> bit<0> ALUctr<0> x 0 1 x 1 0 x 0 1 x 1 0 1 1

1 ALUctr<0> = !ALUop<2> & ALUop<1> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0> CS152 Lec9.28 The ALU Control Block func 6 ALUop 3 ALU Control (Local) ALUctr 3 ALUctr<2> = !ALUop<2> & ALUop<0> + ALUop<2> & !func<2> & func<1> & !func<0> ALUctr<1> = !ALUop<2> & !ALUop<1> + ALUop<2> & !func<2> & !func<0> ALUctr<0> = !ALUop<2> & ALUop<1> + ALUop<2> & !func<3> & func<2> & !func<1> & func<0> + ALUop<2> & func<3> & !func<2> & func<1> & !func<0> CS152 Lec9.29 Step 5: Logic for each control signal nPC_sel <= if (OP == BEQ) then Br else +4 ALUsrc <= if (OP == Rtype) then regB else immed ALUctr <= if (OP == Rtype) then funct elseif (OP == ORi) then OR elseif (OP == BEQ) then sub else add ExtOp <= _____________ MemWr <= _____________ MemtoReg <= _____________ RegWr: <=_____________ RegDst: <= _____________ CS152 Lec9.30 The Truth Table for the Main Control RegDst op

6 Main Control op RegDst ALUSrc MemtoReg RegWrite MemWrite nPC_sel Jump ExtOp ALUop (Symbolic) ALUop <2> ALUop <1> ALUop <0> ALUSrc : ALUop 3 00 0000 R-type 1 0 0 1 0 0 0 x R-type 1 0 0 func 6 ALU Control (Local) ALUctr 3 00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 0 0 x x x 1 1 1 0 x 0 1 x x x 1 1

0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 x x Or Add Add Subtract xxx 0 0 0 x 0 1 0 0 x 0 0 0 0 x 1 CS152 Lec9.32 The Truth Table for RegWrite op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type 1 RegWrite ori 1 lw 1 sw 0 beq 0 jump 0 RegWrite = R-type + ori + lw

= !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> op<5> + !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> (ori) + op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0> (lw) .. op<5> <0> R-type (R-type) .. op<5> <0> ori .. op<5> <0> lw .. op<5> <0> sw .. op<5> <0> beq .. op<0> jump RegWrite CS152 Lec9.33 PLA Implementation of the Main Control op<5> op<5> op<5> op<5> op<5> ..

.. <0> R-type .. <0> ori .. <0> lw .. <0> sw op<5> <0> beq jump .. op<0> RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop<2> ALUop<1> ALUop<0> CS152 Lec9.34 A Real MIPS Datapath (CNS T0) CS152 Lec9.35 Putting it All Together: A Single Cycle Processor ALUop op 6 Instr<31:26> Rt ALUctr busA 0 1 32 ALUSrc

ExtOp Rd MemtoReg MemWr 0 32 Data In 32 Clk Imm16 WrEn Adr 32 Mux 16 Extender imm16 Instr<15:0> 32 Mux 32 Clk Rw Ra Rb 32 32-bit Registers busB 32 ALU busW Zero Rs <0:15> 5 Rt <11:15> 5 Instruction Fetch Unit Clk Rs 3 <16:20> Rt ALUctr

Instruction<31:0> nPC_sel 1 Mux 0 RegWr 5 func Instr<5:0> 6 ALUSrc : ALU Control <21:25> RegDst RegDst Main Control Rd 3 1 Data Memory CS152 Lec9.36 Recap: An Abstract View of the Critical Path (Load) Register file and ideal memory: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: - Address valid => Output valid after access time. Ideal Instruction Memory Instruction Rd Rs 5 5 Instruction Address Imm 16 A PC 32 Clk Rt 5

Clk Rw Ra Rb 32 32-bit Registers 32 32 ALU Next Address Critical Path (Load Operation) = PCs Clk-to-Q + Instruction Memorys Access Time + Register Files Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew B 32 Data Address Data In Ideal Data Memory Clk CS152 Lec9.37 Worst Case Timing (Load) Clk PC Old Value Clk-to-Q New Value Instruction Memory Access Time New Value Rs, Rt, Rd, Op, Func Old Value ALUctr Old Value ExtOp Old Value New Value ALUSrc Old Value New Value

MemtoReg Old Value New Value RegWr Old Value New Value busA busB Delay through Control Logic New Value Register Write Occurs Register File Access Time New Value Old Value Delay through Extender & Mux Old Value New Value ALU Delay Address Old Value New Value Data Memory Access Time busW Old Value New CS152 Lec9.38 Drawback of this Single Cycle Processor Long cycle time: Cycle time must be long enough for the load instruction: PCs Clock -to-Q + Instruction Memory Access Time + Register File Access Time + ALU Delay (address calculation) + Data Memory Access Time + Register File Setup Time + Clock Skew Cycle time for load is much longer than needed for all other instructions CS152 Lec9.39 Preview Next Time: MultiCycle Data Path CPI 1, CycleTime much shorter (~1/5 of time) CS152 Lec9.40 Summary Single cycle datapath => CPI=1, CCT => long 5 steps to design a processor

1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Processor Control is the hard part Input Control Memory MIPS makes control easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Datapath Output CS152 Lec9.41 Where to get more information? Chapter 5.1 to 5.3 of your text book: David Patterson and John Hennessy, Computer Organization & Design: The Hardware / Software Interface, Second Edition, Morgan Kaufman Publishers, San Mateo, California, 1998. One of the best PhD thesis on processor design: Manolis Katevenis, Reduced Instruction Set Computer Architecture for VLSI, PhD Dissertation, EECS, U C Berkeley, 1982. For a reference on the MIPS architecture: Gerry Kane, MIPS RISC Architecture, Prentice Hall. CS152 Lec9.42

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