ET 212 Electronics Field Effect Transistor (FET) Electrical and Telecommunication Engineering Technology Professor Jang Acknowledgement I want to express my gratitude to Prentice Hall giving me the permission to use instructors material for developing this module. I would like to thank the Department of Electrical and Telecommunications Engineering Technology of NYCCT for giving me support to commence and complete this module. I hope this module is helpful to enhance our students academic performance. Outlines Introduction to Field Effect Transistors (FET) JFET Parameters
Biasing JFETs Metal Oxide Semiconductor Field Effect Transistors (MOSFET) Biasing MOSFET Key Words: FET, JFET, Voltage Controlled Device, Pinch Off, Cut Off, MOSFET ET212 Electronics-FETs Floyd 2 FET - Introduction BJTs (bipolar junction transistors) were covered in previous chapters. Now we will discuss the second major type of transistor, the FET (field-effect transistor). Recall that a BJT is a current-controlled device; that is, the base current controls the amount of collector current. A FET is different. It is a voltage-controlled device, where the voltage between two of the terminal (gate and source) controls the current
through the device. The FETs major advantage over the BJT is high input resistance. Overall the purpose of the FET is the same as the BJT. ET212 Electronics-FETs Floyd 3 The JFET The junction field effect transistor, like a BJT, controls current flow. The difference is the way this is accomplished. The JFET uses voltage to control the current flow. As you will recall the transistor uses current flow through the base-emitter junction to control current. JFETs can be used as an amplifier just like the BJT. VGG voltage levels control current flow in the VDD, RD circuit. ET212 Electronics-FETs
Floyd 4 The JFET Figure (a) shows the basic structure of an n-channel JFET (junction field-effect transistor). Wire leads are connected to each end of nchannel; the drain is at the upper end, and the source is at the lower end. Two p-type regions are diffused in the n-channel, and both p-type regions are connected to the gate lead. A representation of the basic structure of the two types of JFET. ET212 Electronics-FETs Floyd JFET schematic symbols. 5 The JFET Basic Operation
Figure shows dc bias voltages applied to an channel device. VDD provides a drain-to-source voltage and supplies current from drain to source. The current is controlled by a field that is developed by the reverse biased gate-source junction (gate is connected to both sides). With more VGG (reverse bias) the field (in white) grows larger. This field or resistance limits the amount of current flow through RD. The JFET is always operated with the gatesource pn junction reverse-biased. ET212 Electronics-FETs Floyd 6 The JFET Basic Operation Effects of VGS on channel width, resistance, and drain current (VGG = VGS).
ET212 Electronics-FETs Floyd 7 JFET Characteristics and Parameters Lets first take a look at the effects with a VGS = 0V. ID increases proportionally with increases of VDD (VDS increases as VDD is increased). This is called the ohmic region (point A to B) because VDS and ID are related by Ohms law. As VDS increases from point B to point C, the reverse-bias voltage from gate to drain (VGD) produces a depletion region large enough to offset the increase in VDS, thus keeping ID relatively constant. The drain characteristic curve of a JFET for VGS = 0 showing pinch-off. ET212 Electronics-FETs
Floyd 8 JFET Characteristics and Parameters Pinch-Off Voltage The point when ID ceases to increase regardless of VDD increases is called the pinch-off voltage (point B). This current is called maximum drain current (IDSS). Breakdown (point C) is reached when too much voltage is applied. This of course undesirable, so JFETs operation is always well below this value. Because breakdown can result in irreversible damage to the device. 9 JFET action that produces the characteristic curve for VGS = 0 V. ET212 Electronics-FETs Floyd
10 JFET Characteristics and Parameters VGS Controls ID From this set of curves you can see with increased voltage applied to the gate the ID is limited and of course the pinch-off voltage is lowered as well. Notice that ID decreases as the magnitude of VGS is increased to larger negative values because of the narrowing of the channel. Pinch-off occurs at a lower VDS as VGS is increased to more negative values. ET212 Electronics-FETs Floyd 11 JFET Characteristics and Parameters VGS Controls ID ET212 Electronics-FETs
Floyd 12 JFET Characteristics and Parameters Cutoff Voltage We know that as VGS is increased ID will decrease. The value of VGS that makes ID approximately zero is the cutoff voltage (VGS(off)). The field (in white) grows such that it allows practically no current to flow through. The JFET must be operated between VGS = 0 and VGS(off). It is interesting to note that pinch-off voltage (VP) and cutoff voltage (VGS(off)) are both the same value only opposite polarity. 13 Comparison of Pinch-Off and Cutoff
As you have seen, there is a difference between pinchoff and cutoff. There is also a connection. VP is the value of VDS at which the drain current becomes constant and is always measured at VGS = 0 V. However, pinch-off occurs for VDS values less than VP when VGS is nonzero. So, although VP is a constant, the minimum value of VDS at which ID becomes constant varies with VGS. VGS(off) and VP are always equal in magnitude but opposite in sign. ET212 Electronics-FETs Floyd 14 Ex. 7-1 For the JFET in Figure, VGS(off) = - 4 V and IDSS = 12 mA. Determine the minimum value of VDD required to put the device in the constantcurrent area of operation. Since VGS(off) = - 4 V, VP = 4 V. The minimum value of VDS for the JFET to be in its constant-current area is
VDS = VP = 4 V In the constant-current area with VGS = 0 V, ID = IDSS = 12 mA The drop across the drain resistor is VRD = IDRD = (12 mA)(560) = 6.72 V Apply Kirchhoffs law around the drain circuit. VDD = VDS + VRD = 4 V + 6.72 V = 10.7 V This is the value of VDD to make VDS = VP and put the device in the constant-current area. ET212 Electronics-FETs Floyd 15 JFET Characteristics and Parameters
JFET Transfer Characteristic Curve The transfer characteristic curve illustrates the control VGS has on ID from cutoff (VGS(off) ) to pinch-off (VP). A JFET transfer characteristic curve is nearly parabolic in shape and can be expressed as VGS I D I DSS 1 V GS ( off ) 2 Example of the development of an n-channel JFET transfer characteristic JFET transfer characteristic curve (n-channel). curve (blue) from the JFET drain characteristic curves (green). Ex. 7-2 A particular p-channel JFET has a VGS(off) = + 4 V. What is ID
when VGS = + 6 V? Ans. ID remains 0. Ex. 7-3 The data sheet for a 2N5459 JFET indicates that typically I DSS = 9 mA and VGS(off) = - 8 V (maximum). Using these values, determine the drain current for VGS = 0 V, -1 V, and 4 V. For VGS = 0 V, ID = IDSS = 9 mA For VGS = - 1 V, 2 2 V 1
V GS 9mA 1 I D I DSS 1 V 8V GS ( off ) 2 For VGS = - 4 V, 9mA1 0.125 9mA 0.766 6.89mA 2 4V 2
I D 9mA 1 9mA1 0.5 9mA 0.25 2.25mA 8V ET212 Electronics-FETs Floyd 17 JFET Biasing Just as we learned that the bi-polar junction transistor must be biased for proper operation, the JFET too must be biased for operation. Lets look at some of the methods for biasing JFETs. In most cases the ideal Qpoint will be the middle of the transfer characteristic curve which is about half of the IDSS. The purpose of biasing is to select the proper dc gate-to-source voltage to establish a desired value of drain current and, thus, a proper Q-point.
ET212 Electronics-FETs Floyd 18 JFET Biasing Self-Bias Self-bias is the most common type of biasing method for JFETs. Notice there is no voltage applied to the gate. The voltage to ground from here will always be VG = 0V. However, the voltage from gate to source (VGS) will be negative for n channel and positive for p channel keeping the junction reverse biased. This voltage can be determined by the formulas below. ID = IS for all JFET circuits. (n channel) VGS = VG VS = -IDRS (p channel) VGS = +IDRS VD = VDD IDRD VDS = VD VS = VDD ID(RD + RS) where VS = IDRS ET212 Electronics-FETs
Floyd 19 Ex. 7-4 Find VDS and VGS in Figure. For the particular JFET in this circuit, the internal parameter values such as gm, VGS(off), and IDSS are such that a drain current (ID) of approximately 5 mA is produced. Another JFET, even of the same type, may not produce the same results when connected in this circuit due the variations in parameter values. VS = IDRS = (5 mA)(68) = 0.34 V VD = VDD IDRD = 15 V (5 mA)(1.0k) = 15 V 5 V = 10 V Therefore, VDS = VD VS = 10 V 0.34 V = 9.66 V Since VG = 0 V,
VGS = VG VS = 0 V 0.34 V = 0.34V ET212 Electronics-FETs Floyd 68 20 JFET Biasing Setting the Q-point of a SelfBiased JFET Setting the Q-point requires us to determine a value of RS that will give us the desired ID and VGS.. The formula below shows the relationship. RS = | VGS/ID | To be able to do that we must
first determine the VGS and ID from the either the transfer characteristic curve or more practically from the formula below. The data sheet provides the IDSS and VGS(off). VGS is the desired voltage to set the bias. ID = IDSS(1 - VGS/VGS(off))2 ET212 Electronics-FETs Floyd 21 Ex. 7-5 Determine the value of RS required to self-bias an n-channel JFET that has the transfer characteristic curve shown in Figure at V GS = - 5 V. From the graph, ID = 6.25 mA
when VGS = - 5 V. Calculate RS. VGS 5V RS 800 ID 6.25mA ET212 Electronics-FETs Floyd 22 Ex. 7-6 Determine the value of RS required to self-bias an p-channel JFET with IDSS = 25 mA and VGS(off) = 15 V. VGS is to be 5 V. 2
V 5 V GS (25 mA) 1 I D I DSS 1 V 15V GS ( off ) (25mA)(1 0.333) 2 11 .1 mA 2
Now, determine RS. VGS 5V RS 450 ID 11 .1 mA ET212 Electronics-FETs Floyd 23 JFET Biasing Voltage-Divider Bias Voltage-divider bias can also be used to bias a JFET. R1 and R2 are used to keep the gate-source junction in reverse bias. Operation is no different from self-bias. Determining ID, VGS for a JFET voltage-divider circuit with VD given can be calculated with the formulas below.
VS I D RS : Source voltage R2 VDD : Gate voltage VG R1 R2 VGS VG VS : Gate-to-source voltage VS ID RS : Drain current ET212 Electronics-FETs VG VGS ID
RS 24 Ex. 7-7 Determine ID and VGS for the JFET with voltage-divider bias in Figure, given that for this particular JFET the internal parameter values are such that V D 7 V. VDD VD 12V 7V 5V ID 1.52mA RD 3.3k 3.3k
Calculate the gate-to-source voltage as follows: VS I D RS (1.52mA)(2.2k) 3.34V R2 1.0 M VDD VG 12V 1.54V 7.8M R1 R2 VGS VG VS 1.54V 3.34V 1.8V ET212 Electronics-FETs
Floyd 25 The MOSFET The metal oxide semiconductor field effect transistor (MOSFET) is the second category of FETs. The chief difference is that there no actual pn junction as the p and n materials are insulated from each other. MOSFETs are static sensitive devices and must be handled by appropriate means. There are depletion MOSFETs (D-MOSFET) and enhancement MOSFETs (EMOSFET). Note the difference in construction. The E-MOSFET has no structural channel. Representation of the basic structure of D-MOSFETs. Representation of the basic E-MOSFET construction and operation (n-channel). The MOSFET Depletion MOSFET The D-MOSFET can be operated in either of two modes the depletion mode or enhancement mode and is sometimes called a
depletion/enhancement MOSFET. Since the gate is insulated from the channel, either positive or a negative gate voltage can be applied. The nchannel MOSFET operates in the depletion mode when a negative gate-tosource voltage is applied and in the enhancement mode when a positive gate-to-source voltage is applied. These devices are generally operated in the depletion mode. 27 The MOSFET Depletion MOSFET Depletion Mode With a negative gate voltage, the negative charges on the gate repel conduction electrons from the channel, leaving positive ions in their place. Thereby, the n channel is depleted of some of its electrons, thus decreasing the channel conductivity. The greater the negative voltage on the gate, the greater the depletion of n-channel electrons. At sufficiently negative gate-to-source voltage, VGS(off), the channel is totally depleted and drain current is zero. Enhancement Mode With a positive gate voltage, more conduction electrons are attracted into the channel, thus increasing
(enhancing) the channel conductivity. ET212 Electronics-FETs Source D-MOSFET schematic symbols. Floyd 28 The MOSFET Enhancement MOSFET (EMOSFET) The E-MOSFET operates only in the enhancement mode and has no depletion mode. It differs in construction from the D-MOSFET in that it has no structural channel. Notice in Figure (a) that the substrate extends completely to the SiO2 layer. For n-channel device, a positive gate voltage above threshold value induces a channel by creating a thin layer of negative charges in the substrate region adjacent to the SiO2 layer, as shown in Figure (b).
Representation of the basic E-MOSFET construction and operation (n-channel). 29 The MOSFET Enhancement MOSFET (E- MOSFET) The schematic symbols for the nchannel and p-channel EMOSFET are shown in Figure below. The conventional enhancement MOSFETs have a long thin lateral channel as shown in structural view in Figure below. n Source
ET212 Electronics-FETs Floyd 30 MOSFET Characteristics and Parameters D-MOSFET Transfer Characteristic As previously discussed, the D-MOSFET can operate with either positive or negative gate voltages. This is indicated on the general transfer characteristic curves in Figure for both n-channel and pchannel MOSFETs. The point on the curves where VGS = 0 corresponds to IDSS. The point where ID = 0 corresponds to VGS(off). As with the JFET, VGS(off) = -VP. D-MOSFET general transfer characteristic curves. Floyd
2 Ex. 7-8 For a certain D-MOSFET, IDSS = 10 mA and VGS(off) = - 8 V. (a) Is this an n-channel or a p-channel? (b) Calculate ID at VGS = - 3 V (c) Calculate ID at VGS = + 3 V. (a) The device has a negative VGS(off); therefore, it is a n-channel MOSFET. 2 2 3V V GS
3.91 mA (b) I D I DSS 1 (10 mA) 1 V 8V GS ( off ) 2 3V 18.9 mA (c) I D 10 mA 1 8V ET212 Electronics-FETs Floyd 32
MOSFET Characteristics and Parameters E-MOSFET Transfer Characteristic The E-MOSFET for all practical purposes does not conduct until VGS reaches the threshold voltage (VGS(th)). ID when it is when conducting can be determined by the formulas below. The constant K must first be determined. ID(on) is a data sheet given value. K = ID(on) /(VGS - VGS(th))2 ID = K(VGS - VGS(th))2 An n-channel device requires a positive gate-to-source voltage, and a p-channel device requires a negative gate-to-source voltage. E-MOSFET general transfer characteristic curves. 33
Ex. 7-9 The data sheet for a 2N7008 E-MOSFET gives ID(o n)= 500 mA (minimum) at VGS = 10 V and VGS(th) = 1 V. Determine the drain current for VGS = 5 V. First, solve for K using Equation, K I D ( on ) (VGS 500 mA 500 mA 2 6 . 17
mA / V VGS (th ) ) 2 10V 1V 2 81V 2 Next, using the value of K, calculate ID for VGS = 5 V. I D K (VGS VGS (th ) ) 2 (6.17 mA / V 2 )(5V 1V ) 2 98.7 mA ET212 Electronics-FETs Floyd 34 MOSFET Biasing D-MOSFET Bias The three ways to bias a MOSFET are zero-bias, voltage-divider bias, and drain-feedback bias. For D-MOSFET zero biasing as the name implies has no applied bias
voltage to the gate. The input voltage swings it into depletion and enhancement mode. Since VGS = 0, ID = IDSS as indicated. VDS = VDD - IDSSRD ET212 Electronics-FETs Floyd 35 Ex. 7-10 Determine the drain-to-source voltage in the circuit of Figure. The MOSFET data sheet gives VGS(off) = - 8 V and IDSS = 12 mA. Since ID = IDSS = 12 mA, the drain-to-source voltage is 560 VDS = VDD IDSSRD = 18 V (12 mA)(560)
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