Building Silicon IP and Sub-Systems for Automotive ...

Building Silicon IP and Sub-Systems for Automotive ...

Building Silicon IP and Sub-Systems for Automotive Infotainment and ADAS Applications Charles Qi System Solutions Architect Embedded TechCon 6/10/2015 Automotive industry: the first and the future Ford Model T in 1915 The First Massively Produced Car Electronic components: Spark plug, headlight, and horn Current supply: Flywheel-mounted magneto 2 2015 Cadence Design Systems, Inc. All rights reserved.. Poster at 2015 SAE Congress Future Self-driving Vehicle Agenda 1. Increased Complexity in Automotive Electronics 2. Scalable DSP Brings High Performance and Flexibility 3. Ethernet, Future Technology of In-car Network 4. Solution for High Performance Memory/IO 5. Sub-System, Key to Reduce Time-to-market 6. Impact of Automotive Qualification and Functional Safety 3 2015 Cadence Design Systems, Inc. All rights reserved.. New applications drive increased complexity Balanced growth in overall automotive semiconductor Significant growth for ADAS and infotainment applications Image courtesy of: BIMMERPOST.com F30 General Vehicle Electronics High-end cars today have more than 100 ECUs! 4 2015 Cadence Design Systems, Inc. All rights reserved.. Increased demand on computation power Over 1000 GOPS required for vision processing Increased Application Complexity

Increased Algorithm Complexity 2020-2025 Self Driving Road Condition Analysis Multi-level Decision HAAR Generalization 2015-2020 Advanced Sensor Fusion Decision Assistant Adaptive Cruise Control Lane Departure Warning Pedestrian Detection HOG SIFT Simple Aid Rear Surround View Night Front View Parking Assist Canny Harris SURF LoG/DoG

Time of Deployment Vision Processing Performance 2500 2156 1900 GOPS 2000 1500 1024 1000 500 256 0 5 SVM 2015 Cadence Design Systems, Inc. All rights reserved.. 350 CNN Increased demand on network/memory bandwidth Increased Network/Memory BW Resolution 100000.0 10000.0 Frame rate 1000.0 100.0 4 streams 10.0 1 stream 1.0

# of stream/camera 1 stream 6 2 streams 4 streams 2015 Cadence Design Systems, Inc. All rights reserved.. Intermediate data Disruption to automotive E/E supply chain Opportunity for silicon and IP vendors to participate at system level EDA/IP EDA/IP Vendors Vendors 7 Tier Tier 22 Semi Semi Tier Tier 11 System System 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are trademarks Cadence Design Inc. in the United States and other countries. All other 2015 Cadence of Design Systems, Inc. Systems, All rights reserved.. trademarks are the property of their respective owners and are not affiliated with Cadence. OEM OEM Agenda 1. Increased Complexity in Automotive Electronics

2. Scalable DSP Brings High Performance and Flexibility 3. Ethernet, Future Technology of In-car Network 4. Solution for High Performance Memory/IO 5. Sub-System, Key to Reduce Time-to-market 6. Impact of Automotive Qualification and Functional Safety 8 2015 Cadence Design Systems, Inc. All rights reserved.. Diversity and complexity of ADAS applications Demands high-performance and flexible compute platform Vision Vision Vision Vision Radar Vision Radar Vision Radar Audio Vision Audio Audio Radar Vision Radar Vision Vision Figure courtesy of: TI Audio/Sound Rear Object Detection Parking Assist/Auto Park Voice Recognition Cabin Noise Reduction Emergency Recognition

9 Vision 2015 Cadence Design Systems, Inc. All rights reserved.. Radar Front Collision Avoidance Braking Adaptive Cruise Control 360 degree Hazard Awareness Rear Collision Detection Vision Rear View Camera Vision Enhancement Auto dimming headlights Blind Spot Detection 360 View Parking Assist Sign Recognition Traffic Signal Detection Lane Detection Rain/Fog Detection Pedestrian Detection Pedestrian Avoidance Eye Focus Detection Driver Monitoring Sign Recognition Vehicle Detection Xtensa offer scalable performance, flexibility Architecture with fully automated HW and SW tools generation Custom Instructions (optional) Set configuration options (optional) Choose processor template Xtensa Processor Generator Xtensa Processor Generator Outputs Hardware EDA scripts RTL

System Modeling / Design Software Tools Instruction Set Simulator (ISS) Xplorer IDE Graphical User Interface to all tools Fast Function Simulator (TurboXim) Synthesis Block Place & Route XTSC SystemC System Modeling Verification Chip Integration / Co-verification To Fab / FPGA 10 Pin-Level Cosimulation XTMP Cbased System Modeling System Development 2015 Cadence Design Systems, Inc. All rights reserved.. GNU Software Toolkit (Assembler, Linker, Debugger, Profiler) Xtensa C/C++ (XCC) Compiler C Software Libraries Operating Systems Software Development

Application Source C/C++ Compile Executable Profile Using ISS Optimize Configuration using Optimize configuration - or Develop options. Custom Instructions Customization of various DSP cores Function-specific Optimization Multiple products, same base architecture and development tools Xtensa Foundation Customize Customize Customize Designer-defined extensions Designer-defined extensions Designer-defined extensions Configure Configure Configure Click-box options Click-box options Click-box options HiFi4 HiFi3

Fusion HiFi EP HiFi Mini HiFi2 ConnX D2, BBE16 BBE32/64EP BSP3 SSP16 Turbo16MS IVP-EP IVP32 Single or Multicore Subsystem Base ISA Base ISA Base ISA Base ISA Optimized DSPs and Controllers Audio Communication s Baseband Imaging and Vision Customize Designer-defined extensions Instruction set Register/state IO queues Memory

Configure Click-box options LX6 Xtensa 11 Applications 11 2015 Cadence Design Systems, Inc. All rights reserved.. Vision DSP Ideal for ADAS Computation Demands Scalable high-performance at low power High Performance AXI I RAM 192x 8b vector 96x16b vector 32x 32b vector I Cache Data RAM IVP-EP Vision Core AXI Micro DMA IVP-EP Vision Core Data RAM 4x 32b scalar 192x 8b vector 96x16b vector

Data RAM Micro DMA I RAM 32x 32b vector I Cache 4x 32b scalar Data RAM VLIW and 64 way SIMD Designed for Multiprocessor 24x power-normalized performance of standard CPU Expandable with TIE Low Power 70mw to <300mW 1/6 the power of standard CPU Small Size Optimized for 40nm, 28nm, and 14-16nm FF technologies the size of a GPU with better power/performance 12 2015 Cadence Design Systems, Inc. All rights reserved.. Rich, vision DSP-optimized software Vision kernel library, standard API, reference applications This roadmap is provided for informational purposes only and does not represent a commitment to deliver any of the features or functionality discussed in the materials. 13 2015 Cadence Design Systems, Inc. All rights reserved.. Agenda 1. Increased Complexity in Automotive Electronics 2. Scalable DSP Brings High Performance and Flexibility

3. Ethernet, Future Technology of In-car Network 4. Solution for High Performance Memory/IO 5. Sub-System, Key to Reduce Time-to-market 6. Impact of Automotive Qualification and Functional Safety 14 2015 Cadence Design Systems, Inc. All rights reserved.. Network technology existed in E/E architecture Mix of low data rate control or high-cost/proprietary solutions Low data rate control Technology Data Rate IP Ownership Media Topology Usage LIN 40kbps LIN Consortium Single wire P2P Body electronics CAN 1Mbps ISO-11898 Bosch UTP Shared Power train (Engine, transmission, ABS)

CAN-FD 2.5Mbps Bosch UTP Shared Power train (Engine, transmission, ABS) FlexRay 10Mbps ISO-17458 FlexRay Consortium UTP Shared High-perf power train, (Safety, drive-by-wire, active suspension, ACC) High cost/proprietary 15 Technology Data Rate IP Ownership Media Topology Usage MOST 150Mbps

SMSC POF Ring infotainment FPDLink LVDS 655Mbps 3Gbps TI/National Shield coax P2P Camera/display 2015 Cadence Design Systems, Inc. All rights reserved.. Ethernet streamlines automotive E/E architecture From low BW, proprietary, control-centric to high BW, standard-based data network Standardization Time synchronization QoS Redundancy VLAN isolation Power efficiency PHY Bandwidth scalability 100Mbps 1Gbps Scales up to 400Gbps Large eco-system Wide deployment Long-lasting part supply Low cost Design to drive UTP Volume drives down ASP CAN-FD/FlexRay CAN-FD/FlexRay Powertrain

Chassis & Safety Gateway MOST CAN Body Electronics 1TPCE Current CAN-FD/FlexRay CAN-FD/FlexRay DCU RTPGE CAN LIN DCU Gateway DCU Infotainment Chassis & Safety RTPGE 1TPCE RTPGE 1TPCE DLC 2015 Cadence Design Systems, Inc. All rights reserved.. 1TPCE/RTPGE DCU RTPGE Powertrain

Body Electronics 16 Infotainment DLC LIN Future DCU ADAS Automotive application endorsed by IEEE standards Change best-effort network to reliable network for automotive AVB: time sync, reserve and guarantee BW TSN: reduce and guarantee latency, redundancy 1588 802.1AS2011 1588: timing and synchronization for time sync network. 802.1AS is Ethernet bridged network profile of 1588 802.1ASREV AS Improvements: one step time stamping, redundant grand master clock and fast failover, redundant sync message path 1722 1722a Layer 2 transport protocol for time-sensitive streams, also known as AVBTP 802.1Qbu Packet preemption 802.1Qav Forwarding and queuing enhancements for time-sensitive streams, traffic class, priority and credit-based shaping

802.1Qbv Time-aware traffic scheduling 802.1Qat Stream reservation protocol (SRP) 802.1Qcc SRP improvements: reduce size/frequency of SRP messaging, interoperation with IGMP 802.1BA AVB network system and AVB profile 802.1CB Frame replication and elimination for reliability Automotive PHY: low-cost, onepair UTP cable, better EMI 17 802.3bw 100Mb/s PHY over single balanced twisted pair cable, also known as 100BASE-T1 15m, 1 pair UTP, full-duplex operation, PAM3 encoding 802.3bp 1Gb/s PHY over single balanced twisted pair cable, also known as 1000BASE-T1 15m, 1 pair UTP, full-duplex operation, PAM3 encoding, RS FEC 2015 Cadence Design Systems, Inc. All rights reserved.. Cadence Automotive Ethernet MAC IP Address in-car network bottleneck with dedicated HW features Scalable Performance Packet Buffer Tx AHB/AXI APB

AHB/AXI master APB DMA Config Reg AVB Queue MAC filter L3/L4 FCS Pause MIB Stats 1588 TSU Rx 100Mbps, 1Gbps data rate Advanced DMA IEEE 802.1Qav QoS MDIO Multiple HW priority queues Credit-based traffic shaping IEEE 1588/802.1AS Time Sync PTP frame detection 1-step or 2-step clock adjustment High-resolution HW time-stamping Power Management Energy Efficient Ethernet state control WoLAN packet detection

Safety and Reliability RGMII RGMII RGMII 18 PCS PCS GMII(MII) TBI 2015 Cadence Design Systems, Inc. All rights reserved.. FCS generation and checking Overrun/underrun error detection Maskable interrupt on error conditions Agenda 1. Increased Complexity in Automotive Electronics 2. Scalable DSP Brings High Performance and Flexibility 3. Ethernet, Future Technology of In-car Network 4. Solution for High Performance Memory/IO 5. Sub-System, Key to Reduce Time-to-market 6. Impact of Automotive Qualification and Functional Safety 19 2015 Cadence Design Systems, Inc. All rights reserved.. LPDDR4 is ideal technology for automotive Solving memory BW demand with optimized cost, power, and reliability High Performance 3200Mbps rate > 20GBps (x32) 2X of LPDDR3 Better SI, Lower EMI Rich training DBI VSS termination 20 LPDDR4: Optimized Memory Solution

Figure courtesy of: Samsung JEDEC Presentation Low cost, long-lasting supply guaranteed by mobile adoption 2015 Cadence Design Systems, Inc. All rights reserved.. Low Power Low-swing I/O DFS support DBI 40% < DDR4 Higher Reliability 1st with PPR Extended op. range Temp compensation Cadence DDR IP Solution DDR Controller IP DDR PHY IP Memory VIP Data Data LPDDR1 LPDDR1 LPDDR2 LPDDR2 LP2NVM LP2NVM LPDDR3 LPDDR3 LPDDR4 LPDDR4 IO Data Data CMD CMD Data Data High performance Multi-queue, request re-ordering, page policy

Advanced reliability features DDR1 DDR1 DDR2 DDR2 DDR3 DDR3 DDR4 DDR4 Wide-IO Wide-IO Combos Combos Data Data DFI Port Port Arbitration Arbitration Command Command Queue Queue Port Port00 Port Portnn DDR Controller IP 16 FF+ DDR IP TC CRC, ECC, inline ECC, BIST Low power features DFS, DFI LPI, power down control per CS, DBI DDR PHY IP Scalable DDR PHY architecture targeting 4266 Mb/s PHY low power states Light sleep/ Deep sleep/Retention

Silicon proven in many generations 28nm, 14-16nm advance nodes Comprehensive Solution LPDDR4/3, DDR4/3 up to 3200 Mb/s Verified with industry-leading memory models Silicon validated full DDR sub-system 21 Cadence Confidential. 2015 Cadence Design Systems, Inc. All rights reserved.. Cadence Camera Interface IP Solution MIPI CSI-2 controller and D-PHY total solution Standard Compliant MIPI CSI-2 v1.1 compliant controller MIPI D-PHY v1.1 compliant PHY High Performance High resolution pixel interface Any lane configuration, x1~ x4 HS 1.5Gbps data transfer per lane Virtual channel support Low Power ULPS and Contention Detection mode Auto termination control for HS and LP modes Reliability Integrated PRBS, CRPAT, CJTPAT Integrated Solution 22 2015 Cadence Design Systems, Inc. All rights reserved..

Pre-integrated and verified Reference VIP integration Reference software drivers FPGA demo platforms Agenda 1. Increased Complexity in Automotive Electronics 2. Scalable DSP Brings High Performance and Flexibility 3. Ethernet, Future Technology of In-car Network 4. Solution for High Performance Memory/IO 5. Sub-System, Key to Reduce Time-to-market 6. Impact of Automotive Qualification and Functional Safety 23 2015 Cadence Design Systems, Inc. All rights reserved.. Sub-system Solution Reduces Customer TTM pre-validated HW/SW reference sub-system ensures integration quality DDR DDR LPDDR LPDDR WideIO WideIO HBM, HBM, HMC HMC SD/eMMC SD/eMMC UFS UFS NAND NAND Flash Flash ONFi, ONFi, TGL TGL Interface IP AFE AFE Ethernet

Ethernet ADC/DAC ADC/DAC CPU/GPU CPU/GPU ARM/x86 ARM/x86 DSP DSP PCIe PCIe Audio/Voice Audio/Voice USB USB Image/video Image/video MIPI MIPI Memory & Storage IP Custom Custom Logic Logic Memory Memory M-PCIe M-PCIe SSIC SSIC SDIO SDIO Peripheral IP Processing IP LDO LDO POR POR

PLL PLL DLL DLL Baseband Baseband HDMI, HDMI, MHL MHL DP/eDP DP/eDP Sensors Sensors PVT PVT AMS/Analog IP VIP support for all major protocols and memory models Systems Systems Peripherals Peripherals Speed-up customer HW/SW integration, ensure product quality and reliability 24 2015 Cadence Design Systems, Inc. All rights reserved.. Example automotive AV sub-systems Representative infotainment and ADAS system topology Ethernet AVB domain Video EP autoE PHY Tensilica Vision AutoE MAC DPHY

CSI-2 PPI MII UTP Centralized ECU for Infotainment or ADAS Video EP autoE PHY Tensilica Vision AutoE MAC DPHY CSI-2 PPI UTP MII AVB switch DDR Audio EP MII AutoE MAC MII UTP eMMC Audio EP 25 I2S

I2S SoundWire Audio DAC AMP Apps PCIe PHY USB USB PHY DSI DPHY autoE PHY Tensilica HiFi AutoE MAC I2S I2S SoundWire Audio DAC AMP AutoE MAC MII PCIe autoE PHY Tensilica HiFi 2015 Cadence Design Systems, Inc. All rights reserved..

UTP Putting the sub-systems into prototyping demos Effective demonstration of integrated sub-systems for automotive Analog audio Audio Sub-system SoC Platform AutoE MAC BRPHY Sound Wire Automotive Head Unit I2S Audio/Video Slimbus Tensilica HiFi DSP Sound Wire Tensilica HiFi Tensilica IVP DSP MIPI Display AutoE AVB switch D-PHY

NFC PCIe Touch SATA AutoE MAC MIPI CSI BRPHY Tensilica Vision Time-sync audio: 2014 IEEE-SA 26 SDIO eMMC Tensilica BBP DSP WiFi DDR DDR USB Comm. LTE DDR Misc intf Ethernet GPS BT Video Sub-system

Apps CPU Automotive Ethernet Face detection: 2015 MWC 2015 Cadence Design Systems, Inc. All rights reserved.. Pedestrian detection: 2015 EVS Unified sub-system development flow Validating every phase of the IP integration 27 2015 Cadence Design Systems, Inc. All rights reserved.. Agenda 1. Increased Complexity in Automotive Electronics 2. Scalable DSP Brings High Performance and Flexibility 3. Ethernet, Future Technology of In-car Network 4. Solution for High Performance Memory/IO 5. Sub-System, Key to Reduce Time-to-market 6. Impact of Automotive Qualification and Functional Safety 28 2015 Cadence Design Systems, Inc. All rights reserved.. Hard IP qualification for AEC-Q100 Increased circuit design and silicon testing effort Hard IP in GDS no long sufficient Production gated by AEC-Q100 qualification Test Item Stringent Test Requirements Large Sample Size ELFR

Grade 0: 48 hours at 150C or 24 hours at 175C Grade 1: 48 hours at 125C or 24 hours at 150C Grade 2: 48 hours at 105C or 24 hours at 125C Grade 3: 48 hours at 85C or 24 hours at 105C 3 lots, 800 parts per lot HTOL Grade 0: +150C Ta for 1000 hours Grade 1: +125C Ta for 1000 hours Grade 2: +105C Ta for 1000 hours Grade 3: +85C Ta for 1000 hours 3 lots, 77 parts per lot ESD (HBM) Classification 2 or better Conducted at 500V, 1000V and 2000V Some product might require up to 7000V (# of 250V voltage steps) x 3 ESD (CDM) Classification C4B or better 750V corner pins, 500V for all other pins (# of 250V voltage steps) x 3 Latch-up Negative/positive current and over voltage testing 6 parts from 1 lot Characterization CHAR plan should cover PPM target, corner lots, sample sizes, etc. No hard-specific requirements provided Multiple parts from corner lots # driven by test accuracy

29 2015 Cadence Design Systems, Inc. All rights reserved.. IP development for functional safety Enhancing design process, tool qualification, and HW features ISO26262 provides requirements at system level Requirements propagate down to IP developments 30 2015 Cadence Design Systems, Inc. All rights reserved.. Conclusion 31 2015 Cadence Design Systems, Inc. All rights reserved.. 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, Palladium, and Xtensa are registered trademarks and Protium is a trademark of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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